Mô tả công việc
- 3+ years experiences in physical design – DFT/STA.
- Familiarity with simulation, debugging tools, and working closely with design and verification team.
- Experience with multi-clock and multi-power domain designs.
- Familiarity with DFT insertion, and multi-mode timing constraints.
- Familiarity with hierarchical design approach, top-down design, timing and physical convergence.
- Experience with design synthesis and backend STA closure.
- Deep understanding of designs’ constraints development.
- Good understanding of AC timing from specs to implementation.
- Good understanding of DFT modes and their constraints.
- Able to setup full chip Level Timing Constraint.
- Programming in Perl, Tcl and C++ is a plus.
Yêu cầu ứng viên
- Good at English communication.
- Ph.D/MS degree is not required, but preferred.
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