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As a Design Verification (DV) Engineer, you are the "Gatekeeper" of our silicon quality. Your mission is to act as a critical "bug hunter," ensuring that the RTL Design matches the architectural specifications perfectly. You will develop sophisticated verification environments and test scenarios to stress-test the design, identifying even the most hidden vulnerabilities before the chip moves to the tape-out stage. A high-quality DV process saves millions of dollars and ensures the success of our "Make in Vietnam" chips.

KEY RESPONSIBILITIES

1. Verification Planning:

• Analyze design specifications (Specs) to understand the architecture, functionality, and performance requirements.
• Develop comprehensive verification plans, defining test strategies and identifying critical "corner-case" scenarios.

2. Testbench Development:

• Design and implement scalable, automated verification environments using SystemVerilog and UVM (Universal Verification Methodology).
• Develop verification components including Drivers, Monitors, Scoreboards, and Sequencers to automate the checking process.

3. Execution & Bug Hunting:

• Execute simulations to verify the RTL code against the design intent.
• Perform deep-dive debugging to identify root causes of failures and work closely with RTL Designers to resolve issues.
• Run regression tests to ensure that new code changes do not break existing functionalities.

4. Coverage Closure:

• Analyze Code Coverage and Functional Coverage to ensure 100% verification of the design.
• Produce detailed verification reports and assess the readiness of the design for tape-out.